ASIC • FPGA • 3D‑IC • EDA • AI Hardware
Advanced Semiconductor & AI Hardware Consulting
Independent consulting focused on ASIC & FPGA design, 3D‑IC integration, and EDA flow optimization — with hands‑on acceleration for AI/ML workloads (NVIDIA stack, D‑Matrix). Engagements from architecture to bring‑up, performance, and design closure.
Start a conversation →About
Operating since 2014 under Jerome Ribo Consulting and now as JR Consulting Tech, the practice serves startups and established semiconductor teams across architecture, design, and verification. Experience spans high‑speed I/O (SERDES/CDR), advanced packaging, and tool flow tuning across leading EDA platforms.
2014→Now
Independent practice
ASIC / FPGA
Design & bring‑up
3D‑IC
Flow & integration
Services
- ASIC & FPGA Design — architecture, RTL, verification, timing closure, and bring‑up.
- 3D‑IC Integration & EDA Flow Optimization — packaging, partitioning, floorplanning, and tool tuning.
- AI/ML Hardware Acceleration — NVIDIA stack and D‑Matrix flows; model‑to‑silicon performance work.
- High‑Speed Interfaces — SERDES, CDR, memory subsystems; signal integrity considerations.
- Prototyping & Performance — FPGA prototyping, profiling, and optimization.